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front-end for am/fm receivers up-conversion architecture for am high speed pll with inlock detector for optimized rds applications single frequency reference for am/fm am/fm station detector m p-controlled compensation of ex- ternal components spread adjustable audio mute fully programmable by i 2 c bus advanced bicmos technology general description the TDA7421 is a high performance tuner circuit that integrates am/fm sections, if counter and pll synthesizer on a single chip. use of bicmos technology allows the implemen- tation of tuning functions with a minimum of exter- nal components. value spread of external components can be fully compensated by means of on-chip electrical ad- justment controlled by external m p. the automatic gain control (agc) operates on different sensitivities and bandwidths in order to improve sensitivity and dynamic range. i 2 c bus allows to control selected functions of the tuner (agc and amplifiers gain, pll and counters op- eration modes). june 1998 1 2 3 5 6 4 7 8 9 10 27 11 28 29 30 31 32 59 58 57 56 54 55 53 52 51 50 49 43 42 41 39 38 40 48 47 46 44 45 fm agc out fm rf agc in fm mix in + am mix1 in + am mix1 in - fm mix in - xtal d osc gnd vco e rf gnd vco b pll gnd sleep sda scl dig gnd dig vdd ifc sstop am stereo out cln gnd if2 gnd am agc2 tc am det fm if agc in am mix2 in + am mix2 in- rf vcc am mix2 out - am mix2 out + fm if amp1 in + fm if amp1 in - fm if amp1 out fm if amp2 in + fm if amp2 in - fm bw tc fm mute drive fm smeter am smeter fm det adj fm quad+ fm sd am sd fm if amp2 out if1 vcc fm lim in + if1 gnd fm lim in - d96au546a 22 23 24 25 26 60 mix out - 61 mix out + 62 am agc1 tc 63 am agc1 rf amp 64 am agc1 pin lp out lp in1 lp in2 lp in3 pll vref 17 18 19 20 21 37 36 34 33 35 fm quad- if2 vcc am ref am bpf am if2 in 12 13 14 15 16 pll vcc fm rf adj fm ant adj xtal g osc vcc audio out pins connection tqfp64 ordering number: TDA7421 TDA7421 am/fm tuner for car radio and hi-fi applications ? 1/38
am rf agc am mix in+ am mix in- agc1 ant am agc1 rf amp out am agci tc am mix2 in+ am mix2 in- am mix2 out- am mix2 out+ am detector am if agc am if2 in am ifref am bpf am if counter am det am agc2 tc i 2 c bus sda scl d96au540a filter adj. sleep filter adj. fm agc filter adj. fm mix in+ fm mix in- vcoe vcob xtalg xtald fm agc out fm rf agc in mix out- mix out+ fm if amp1 in- fm if amp1 in+ fm if amp1 out phase comparator fm if amp2 in+ fm if amp2 out charge pump - lim in- triple out am smeter am if ifc sstop am stereo out lpin2 lpin1 lpin3 lpout pll v cc pll vref pll gnd - + fm if agc in fm if amp2 in- lim in+ fm if counter quadrature detector am quad+ quad- slider detuning detector s meter adjacent ch. det. adjacent ch. mute stop station detuning mute soft mute fm mute + 4 bit dac + 4 bit dac fm rf adj fm ant adj audio out am smeter fm smeter fm det adj out am sd/ fm sd bw tc limiter am if count am sd fm sd vco 10.25mhz osc lock det fm block diagram TDA7421 2/38
thermal data symbol parameter value unit r th j-amb thermal resistance junction-ambient typ. 68 c/w pin description n. name function 1 am mix1 in - input "-" to the am 1st mixer (differential input) 2 am mix1 in + input "+" to the am 1st mixer (differential input) 3 fm mix in - input "-" to the fm mixer (differential input) 4 fm mix in + input "+" to the fm mixer (differential input) 5 fm rf agc in input to the rf agc circuit 6 fm agc out voltage output to the fm agc 7 rf gnd rf circuits ground 8 vco b local oscillator input to the transistor base (two-pin oscillator) 9 vco e local oscillator input to the transistor emitter (two-pin oscillator) 10 osc gnd oscillator ground 11 xtal d crystal oscillator input to mos drain (two-pin oscillator) 12 xtal g crystal oscillator input to mos gate (two-pin oscillator) 13 osc vcc oscillator positive supply 14 fm ant adj tuning varicap voltage for antenna fm filter 15 fm rf adj tuning varicap voltage for rf fm filter 16 pll vcc pll positive supply 17 lp out op amp output to pll loop filters 18 lp in1 pll "n. 1" loop filter connection to op amp inverting input 19 lp in2 pll "n. 2" loop filter connection to op amp inverting input 20 lp in3 pll "n. 3" loop filter connection to op amp inverting input 21 pll vref voltage reference to op amp noninverting input 22 pll gnd pll ground 23 sleep i 2 c bus disconnect signal 24 sda i 2 c bus data 25 scl i 2 c bus clock absolute maximum ratings symbol parameter value unit t amb operating temperature range -40 to 85 c t stg storage temperature range -55 to 150 c v cc analog supply voltages (pll, rf, if1, if2, osc) 10.2 v v dd digital supply voltage 5.5 v TDA7421 3/38
pin description (continued) n. name function 27 dig gnd digital circuits ground 28(*) ifc sstop am stereo out search stop signal or output (single ended) of am if amplifier 29 cln gnd "clean" ground 30 if2 gnd if 2nd ground 31 am agc2 tc am 2nd agc time constant 32 am det connection to the capacitor of the am diode-capacitor detector 33 am bpf connection to the am if filter 34 am ref reference voltage of am if amplifier 35 am if2 in input (single ended) of am 2nd if amplifier 36 if2 vcc if 2nd positive supply 37 fm quod - "-" insertion pt. of fm quadrature network (differential) 38 fm quad + "+" insertion pt. of fm quadrature network (differential) 39 audio out audio frequency output (single ended) 40 (*) fm sd am sd fm station detector output or am station detector output 41(*) fm smeter am smeter fm det adj fm s-meter output or am s-meter output or fm detuning adjustment 42 fm mute drive fm mute time constant 43 fm bw tc fm detuning detector time constant 44 if1 gnd if 1st ground 45 fm lim in - input "-" of fm limiter (differential input) 46 fm lim in + input "+" of fm limiter (differential input) 47 if1 vcc if 1st positive supply 48 fm if amp2 out output (single ended) of the fm if 2nd amplifier buffer 49 fm if amp2 in - input "-" of the fm if 2nd amplifier (differential input) 50 fm if amp2 in + input "+" of the fm if 2nd amplifier (differential input) 51 fm if amp1 out output (single ended) of the fm if 1st amplifier buffer 52 fm if amp1 in - input "-" of the fm if 1st amplifier (differential input) 53 fm if amp1 in + input "+" of the fm if 1st amplifier (differential input) 54 am mix2 out - output "-" of the am 2nd mixer (differential output) 55 am mix2 out + output "+" of the am 2nd mixer (differential output) 56 rf vcc rf stage positive supply 57 am mix2 in - input "-" to the am 2nd mixer (differential input) 58 am mix2 in + input "+" to the am 2nd mixer (differential input) 59 fm if agc in input fm if agc circuit 60 mix out - output "-" of the fm/am 1st mixer (differential output) 61 mix out + output "+" of the fm/am 1st mixer (differential output) 62 am agc1 tc am 1st agc time constant 63 am agc1 rf amp voltage output of the am 1st agc, to the transistor of the rf af amplifier 64 am agc1 pin current output of the am 1st agc, to the pin diodes antenna am attenuator (*) pin function is user-defined by software. TDA7421 4/38
electrical characteristics dc parameters (t amb = 25c; v cc = 8.5v, v dd = 5v unless otherwise specified) symbol parameter test condition min. typ. max. unit dig v dd digital supply voltage 4.75 5.25 v dig i dd digital supply current am mode 4.0 4.6 5.2 ma fm mode 3.5 4.0 4.5 ma pll v cc pll supply voltage 7.5 10 v pll i cc pll supply current am mode 1.2 1.6 2.0 ma fm mode 2.5 3.0 3.5 ma rf v cc rfsupply voltage 7.5 10 v rf i cc rf supply current am mode 15.0 17.5 20.0 ma fm mode 10.0 13.0 16.0 ma if1 v cc if1 supply voltage 7.5 10 v if1 i cc if1 supply current am mode 2.2 2.7 3.2 ma fm mode 16.0 19.5 23.0 ma if2 v cc if2 supply voltage 7.5 10 v if2 i cc if2 supply current am mode 8.5 10.5 12.5 ma fm mode 27.0 32.0 37.0 ma osc v cc oscillator supply voltage 7.5 10 v osc i cc oscillator supply current am mode 14.5 17.0 19.5 ma fm mode 11.0 14.0 17.0 ma total i cc total supply current am mode 45.0 50.0 55.0 ma fm mode 73.0 81.0 89.0 ma symbol parameter test condition min. typ. max. uni f vcomin minimum vco frequency v turn = 0, europe/usa japan 80.9 55 98.2 65.4 mhz mhz f vcomax maximum vco frequency v turn = v cc , europe/usa japan 123.2 79.2 128 90 mhz mhz v osc oscillator amplitude fosc = 108.8mhz, europe/usa f osc = 72.3mhz, japan 106 dbu ac parameters ref: fm test circuit measure v osc with high impedance fet probe voltage controlled oscillator (vco) symbol parameter test condition min. typ. max. uni f xtal reference frequency 10.25 mhz v xtal oscillator amplitude 108 dbu reference oscillator ref: am test circuit measure v xtal with high impedance fet probe TDA7421 5/38
symbol parameter test condition min. typ. max. uni s+n/n signal to noise ratio 68 db thd total harmonic distortion deviation = 40khz 0.3 % v o af audio output level 350 400 450 mv rms us usable sensitivity antenna level at which s+n/n=30db 4dbu agc range range agc fm 65 db electrical characteristics (continued) fm section global performances refer to evaluation circuit and enclosed curves (s+n/n, thd) - rf input: f c = 98.1mhz, 75khz dev., 1khz mod.,60dbu - audio output: bpf 20hz - 20khz fm agc ref: fm test circuit, measure input at v fmrfagcin , and v fmifagcin , output at v fmagcout symbol parameter test condition min. typ. max. unit v rfagcstart open loop rf agc starting point f rfagcin = 98.1mhz value of v fmrfagcin , at which v fmagcout = 4v 74 80 86 dbu r inrfagc input resistance 20 k w v ifagcstart open loop if agc starting point f ifagcin = 10.7mhz value of v fmifagcin , at which v fmagcout = 4v fagc2-0 set to 111 71 77 83 dbu r inifagc input resistance 20 k w r outfmagc output resistance 10 k w fm mixer ref: fm test circuit, measure input at v mixfmin , output at v mixout symbol parameter test condition min. typ. max. unit z in,mix single-ended input impedance (pin 3, pin4) f = 100mhz 12 w g mix conversion gain f in = 98.1mhz 21.8 db ip3 mix 3rd order intermodulation distortion intercept point f d = 98.1mhz; f u1 = 98.2mhz; f u2 = 98.3mhz; 104 dbu cp1 mix 1db compression point f in = 98.1mhz 90 dbu symbol parameter test condition min. typ. max. uni antadj max off maximum fm antenna filter adjustment voltage offset v pllout = 2.5v, ana3-0 set to 1111 21 25 27 % antadj step off fm antenna filter adjustment voltage offset step v pllout = 2.5v, ana3-0 set to 1001 2.8 3.6 4.4 % rfadj max off maximum fm rf filter adjustment voltage offset v pllout = 2.5v, rfa3-0 set to 1111 21 25 27 % rfadj step off fm rf filter adjustment voltage offset step v pllout = 2.5v, rfa3-0 set to 1001 2.8 3.6 4.4 % fm front-end electrical adjustments ref: fm test circuit measure v antadj and v rfadj referred to v pllout TDA7421 6/38
electrical characteristics (continued) fm if amplifier 1 ref: fm test circuit, measure input at v fmamp1in , output at v fmamp1out symbol parameter test condition min. typ. max. unit r in,amp1 input resistance f = 10.7mhz 330 w r out,amp1 output resistance f = 10.7mhz 330 w g typ,amp1 typical gain f in = 10.7mhz, fbh3-0 set to 0100 16.5 17.5 18.5 db g min,amp1 minimum gain f in = 10.7mhz, fbh3-0 set to 0001 14.5 15.5 16.5 db g max,amp1 maximum gain f in = 10.7mhz, fbh3-0 set to 0000 18.5 19.5 20.5 db ip3 amp1 3rd order intermodulation distortion intercept point f d = 10.7mhz; f u1 = 10.8mhz; f u2 = 10.9mhz, fbh3-0 set to 0100 109 dbu cp1 amp1 1db compression point f in = 10.7mhz; fbh3-0 set to 0100 96 dbu fm if amplifier 2 ref: fm test circuit, measure input at v fmamp2in , output at v fmamp2out symbol parameter test condition min. typ. max. unit r in,amp2 input resistance f = 10.7mhz 330 w r out,amp2 output resistance f = 10.7mhz 330 w g typ,amp2 typical gain f in = 10.7mhz, fbl3-0 set to 0100 5 6 7 db g min,amp2 minimum gain f in = 10.7mhz, fbl3-0 set to 0001 3 4 5 db g max,amp2 maximum gain f in = 10.7mhz, fbl3-0 set to 0000 7 8 9 db ip3 amp2 3rd order intermodulation distortion intercept point f d = 10.7mhz; f u1 = 10.8mhz; f u2 = 10.9mhz, fbl3-0 set to 0100 122 dbu cp1 amp2 1db compression point f in = 10.7mhz; fbl3-0 set to 0100 110 dbu fm limiter, field strengh meter and demodulator ref: fm test circuit, measure: - input at v fmlimin , f in = 10.7mhz - filtered fs meter output at v sm,filt - shifted fs meter output at v sm,shift (fmadj set to 0) - demodulator adjustment output at v sm,shift (fmadj set to 1) symbol parameter test condition min. typ. max. unit r in,lim limiter input resistance 330 w g lim limiter gain 90 db ls limiting sensitivity 23 dbu sm1 smeter 1 at v sm,filt v fmlimin = 42dbu 0.1 (1) 0.25 0.5 (1) v sm2 smeter 2 at v sm,filt v fmlimin = 77dbu 2.4 (1) 2.75 3.1 (1) v sm3 smeter 3 at v sm,filt v fmlimin = 102dbu 4.0 (1) 4.35 4.7 (1) v sm minshift smeter minimum shift voltage at v sm,shift referred to v sm,filt v fmlimin = 70dbu, fsl4-0 set to 00000 0.25 0.3 0.35 v sm maxshift smeter maximum shift voltage at v sm,shift referred to v sm,filt v fmlimin = 70dbu, fsl4-0 set to 11111 1.55 1.8 2.05 v g dem demodulator conversion gain v fmlimin > ls 2 mv rms / khz g demadj demodulator adjustment conversion gain v fmlimin > ls, measured at v smshift , fmadj set to 1 14 mv rms / khz note1: refer to global application circuit; input at first ceramic filter in, fbh3-0 set to 0001, fbl3-0 set to 0001 TDA7421 7/38
electrical characteristics (continued) fm audio amplifier ref: fm test circuit, measure: - input at v fmlimin , = 95dbu, f in = 10.7mhz - audio output at v audio , bpf 20hz to 20khz - muting voltage at v mute, drive symbol parameter test condition min. typ. max. unit v mute mute voltage v mute,drive for which d v af = - 29db, fmhigh set to 0, aum2-0 set to 111 2v v play play voltage v mute,drive for which d v af = - 1db, fmhigh set to 0, aum2-0 set to 111 0.3 v g amp,play audio amplifier gain in play conditions v mute,drive < v play 9db g amp,mutemax audio amplifier highest gain in mute condition v mute,drive > v mute , fmhigh set to 1, aum2-0 set to 001 6.5 db g amp,mutemin audio amplifier lowest gain in mute condition v mute,drive > v mute , fmhigh set to 0, aum2-0 set to 111 -21 db v af af output level f dev = 75khz, f mod = 1khz, v mute,drive < v mute 350 (1) 400 450 (1) mv rms thd aftotal harmonic distortion f dev = 75khz, f mod = 1khz, v mute,drive < v mute 0.5 % s+n/n af signal to noise ratio f dev = 75khz, f mod = 1khz, v mute,drive < v mute 68 (1) 75 % amr amplitude modulation rejection am modulation deph 30%, f mod = 1khz, with respect to fm modulated signal with f dev = 40khz, v mute,drive < v mute 60 (1) 67 db audio curr audio out current capability 5 ma mute r out mute drive output resistance 1 k w note1: refer to global application circuit; input at first ceramic filter in, fbh3-0 set to 0001, fbl3-0 set to 0001 fm quality detectors field strength detector ref: fm test circuit, measure: - input at v fmlimin , f in = 10.7mhz, cw - output at v mute,drive symbol parameter test condition min. typ. max. unit fsd min field strenght detector minimum threshold v fmlimin level at which v mute,drive = v mute , fsm3-0 set to 0000 40 dbu fsd max field strenght detector maximum v fmlimin level at which v mute,drive = v mute , fsm3-0 set to 1111 60 dbu TDA7421 8/38
electrical characteristics (continued) detuning detector ref: fm test circuit, measure: - inputs at v fmlimin , cw - output at v mute,drive symbol parameter test condition min. typ. max. unit dd start detuning detector starting point fr equency shift from 10.7mhz at which v mute,drive = v play 23 khz dd slope,min detuning detector minimum muting slope frequency shift from 10.7mhz + dd start, at which v mute,drive = v mute, bwm2-0 set to 100, fmrecseek set to 0 22.5 30 37.5 khz dd slope,max detuning detector maximum muting slope frequency shift from 10.7mhz + dd start, at which v mute,drive = v mute, bwm2-0 set to 001, fmrecseek set to 0 7.5 10 12.5 khz dd trc detuning detector time constant ratio ratio of "reception" mode integration time constant inside the detuning detector with respect to "seek" mode 34/6 s/s adjacent channel detector ref: fm test circuit, measure: - inputs at v fmlimin : desired 10.7mhz, 95dbu cw; undesired 10.8mhz cw - output at v mute,drive - bwm2-0 set to 001 symbol parameter test condition min. typ. max. unit acd max adjacent channel quality detector maximum sensitivity threshold amplitude of undesired signal at which v mute,drive = v mute , hdm4-0 set to 11111 91 dbu acd min adjacent channel quality detector minimum sensitivity threshold amplitude of undesired signal at which v mute,drive = v mute , hdm4-0 set to 00000 94.8 dbu field strength station detector ref: fm test circuit, measure: - inputs at v fmlimin : desired 10.7mhz, cw - output at v fmsd - fmrecseek set to 1 symbol parameter test condition min. typ. max. unit fssd min field strength station detector minimum threshold v fmlimin level at which v fmsd = 2.5, fsm4-0 set to 00000 24 dbu fssd max field strength station detector maximum threshold v fmlimin level at which v fmsd = 2.5, fsm4-0 set to 11111 76 dbu detuning station detector ref: fm test circuit, measure: - input at v fmlimin , cw; - output at v fmsd - fmrecseek set to 1 symbol parameter test condition min. typ. max. unit dsd detuning station detector threshold frequency shift from 10.7mhz at which v fmsd = 2.5v 23 khz TDA7421 9/38
electrical characteristics (continued) adjacent channel station detector ref: fm test circuit, measure: - input at v fmlimin : desired 10.7mhz, 95dbu cw; undesired 10.8mhz cw - output at v fmsd - fmrecseek set to 1 symbol parameter test condition min. typ. max. unit acsd max adjacent channel detector maximum sensitivity threshold amplitude of undesired signal at which v fmsd = 2.5v, hdm4-0 set to 11111 92.5 dbu acd min adjacent channel detector minimum sensitivity threshold amplitude of undesired signal at which v fmsd = 2.5v, hdm4-0 set to 00000 94.9 dbu am section global performances refer to evaluation circuit and enclosed curves (s+n/n, thd) - rf input: f c = 1mhz, f mod = 1khz, m = 0.3; - audio output: bpf 20hz - 20khz symbol parameter test condition min. typ. max. unit v in min maximum sensitivity v inrf = 74dbu; d v af = - 20db 20 dbu v in us usable sensitivity s+n/n = 20db 31 dbu d v is agc range v inrf = 74dbu; d v af = -10db 50 db s+n/n signal to noise ratio v inrf = 74dbu 46.0 53.0 db a imag image rejection f 1 = 1.9mhz f 2 = 22.4mhz db a tw tweet v inrf = 74dbu; f1 = 900khz; f2 = 1350khz 1.2 db thd total harmonic distortion v inrf = 74dbu; m = 0.3 0.45 1.0 % v inrf = 74dbu; m = 0.8 1.73 % v inrf = 120dbu; m = 0.3 0.33 % v af audio output level v inrf = 74dbu 137 167 197 mv rms v amst am if2 output level v inrf = 74dbu 106 dbu am mixer 1 ref: am test circuit, measure input at v mix2amin , output at v mixout symbol parameter test condition min. typ. max. unit r inmix1 input resistance 1.2 k w g mix1 conversion gain f in = 1mhz 7.5 8.5 9.5 db ip3 mix1 3rd order intermodulation distortion intercept point f d = 1mhz; f u1 = 1.1mhz; f u2 = 1.2mhz; 115 dbu cp1 mix1 1db compression point f in = 1mhz 98.7 dbu TDA7421 10/38
electrical characteristics (continued) am wide & narrow agc ref: am test circuit, input at v mix1amin , and v mix2amin , output at v amagc1amp , andv amagc1pin symbol parameter test condition min. typ. max. unit v wagctyp open loop wide agc typical starting point f wagcin = 1mhz, aag3-0 set to 1000; v mix1amin at which v amagc1amp = 2.5v 91.3 dbu v wagcmin open loop wide agc minimum starting point f wagcin = 1mhz, aag3-0 set to 0000; v mix1amin at which v amagc1amp = 2.5v 80.6 dbu v wagcmax open loop wide agc maximum starting point f wagcin = 1mhz, aag3-0 set to 1111; v mix1amin at which v amagc1amp = 2.5v 95.6 dbu v nagctyp open loop narrow agc typical starting point f nagcin = 10.7mhz, aag3-0 set to 1000; v mix2amin at which v amagc1amp = 2.5v 93.2 dbu v nagcmin open loop narrow agc minimum starting point f nagcin = 10.7mhz, aag3-0 set to 0000; v mix2amin at which v amagc1amp = 2.5v 82.8 dbu v nagcmax open loop narrow agc maximum starting point f nagcin = 10.7mhz, aag3-0 set to 1111; v mix2amin at which v amagc1amp = 2.5v 97.4 dbu r outamagc1 output resistance 23.3 k w i amagc1pin maximum pin-diode current f wagcin = 1mhz; v mix1amin = 90dbu; aag3-0 set to 0000 1.4 ma am mixer 2 ref: am test circuit, measure input at v mix2amin , output at v mix2out , (switches must be in position 2 for agc measurements). symbol parameter test condition min. typ. max. unit r inmix2 input resistance 5 k w g mix2 maximum conversion gain f in = 10.7mhz 19.6 db ip3 mix2 3rd order intermodulation distortion intercept point f d = 10.7mhz; f u1 = 10.8mhz; f u2 = 10.9mhz; 122 dbu cp1 mix2 1db compression point f in = 10.7mhz 90.7 dbu agc mixcp central point of agc2 intevention on mixer 2 f in = 10.7mhz; v mix2amin = 52dbu; value of v mix2out 61.2 dbu agc mixsp agc2 starting point on mixer 2 f in = 10.7mhz; value of v mix2amin for which v mix2out is agc mixcp - 3db 40 dbu agc mixr agc2 range on mixer 2 f in = 10.7mhz; range of v mix2amin for which v mix2out is agc mixcp 3db 24 db TDA7421 11/38
electrical characteristics (continued) am if2 amplifier ref: am test circuit, measure input at v ip2ampin , output at v ip2ampout , (switches must be in position 1), f in = 450khz. symbol parameter test condition min. typ. max. unit r in,if2amp input resistance 2 k w g if2amp maximum gain v if2ampin = 10dbu 51 db agc ampcp central point of agc2 intevention on if2 amp v if2ampin = 72dbu; value of v if2ampout 115 dbu agc ampsp agc2 starting point on if2 amp value of v if2ampin for which v if2ampout is agc ampcp - 3db 63 dbu agc ampr agc2 range on if2 amp f in = 10.7mhz; range of v mix2amin = for which v mix2out is agc mixcp 3db 36 db agc tcr agc2 time constant ratio ratio of agc2 "reception" time constant and "seek" time constant 150/5 s/s if amst am if2 output level at pin 28 v if2ampin = 72dbu; amstereo set to 1 104 106 108 dbu if amstcurr current capability of pin 28 amstereo set to 1 150 m a am field strength meter and field strength station detector ref: am test circuit, measure at v mix2amin , outputs at v amsmeter and at v amsd (switches in position 2), - f in = 10.7khz. - amseek set to 1 symbol parameter test condition min. typ. max unit amsm1 am smeter 1 at v amsmeter v mix2amin = 35dbu 2.2 2.89 3.6 v amsm2 am smeter 2 at v amsmeter v mix2amin = 65dbu 2.5 3.26 4.0 v amsm3 am smeter 3 at v amsmeter v mix2amin = 95dbu 3.0 3.73 4.5 v amsd min station detector minimum threshold v mix2amin at which v amsd = 2.5v, ass3-0 set to 0000 44 dbu amsd max station detector maximum threshold v mix2amin at which v amsd = 2.5v, ass3-0 set to 1111 64 dbu if counter output ref: am & fm test circuit, measure at pin 28 symbol parameter test condition min. typ. max unit ifc fm fm ifc sensitivity v fmlimin at which vpin 28 = 2.5v, fmrecseek set to 1, ew2-0 set to 101, ifs2-0 set to 010 34 dbu ifc am am ifc sensitivity v if2ampin at which vpin 28 = 2.5v, amseek set to 1, ew2-0 set to 011, if2-0 set to 100, amfm stby1-0 set to 10 29 dbu ifc current ifc current capability 150 m a TDA7421 12/38
electrical characteristics (continued) loop filter input output (lp_in1, lp_in2, lp_in3, lp_out) symbol parameter test condition min. typ. max. unit -i in input leakage current v in = gnd; pd out = tristate 1) -2 0 2 m a i in input leakage current v in = v dd ; pd out = tristate -2 0 2 m a v ol output voltage low i in = -0.2ma; v cc = 8.5v 0.5 v v oh output voltage high i out = 0.2ma; v cc = 8.5v 8 v i out output current sink v pll = 8.5v; 10 ma i out output current source vout = 0.5 to 8v 10 ma i 2 c bus interface symbol parameter test condition min. typ. max unit f scl scl clock frequency 100 500 khz t aa scl low to sda data valid 300 ns t buf time the bus must be free for the new transmission 4.7 m s t hd-sta start condition hold time 4.0 m s t low clock low period 4.7 m s t high clock high period 4.0 m s t su-sda start condition setup time 4.7 m s t hd-dat data input hold time 0 m s t su-dat date input setup time 250 ns t r sda & scl rise time m s t f sda & scl full time m s t su-sto stop condition setup time 4.7 m s t dh data out time 300 ns v il input low voltage 1v v ih input high voltage 3 v (1) depends upon filter circuitry (2) depends upon application circuit (3) depends only upon if2 ceramic filter TDA7421 13/38
t2 15pf 15pf 1m vxtal 11 12 1 2 agc2 det agc w & n + - 2k 60 61 330 v mixout v mix1amin 2k v if2ampin v mix2amin 57 54 58 55 v if2ampout 35 34 33 40 41 32 31 63 64 i amagc1pin v amagc1rfamp v amsd v amsmeter d97au803a 1 2 2 1 v cc v cc t3 am test circuit t2 22pf 15pf 1.8k l2 8 9 3 4 demod fm agc + - 330 60 61 330 v mixout v tun v fmlimin v fmifagcin 52 59 31 46 45 40 41 39 5 6 v fmsd v smshift d97au804a v mixfmin t1 1:3.5 v fmrfagcin v fmagcout 10nf 10nf 68pf v1 v tun 5k v cc 10nf 53 v fmamp1in 51 330 10nf 10nf 10nf + - 330 49 50 v fmamp2in 48 330 10nf 10nf 10nf v fmamp1out 330 330 v fmamp2out + - 10nf 10nf 330 l6 audio 38 37 v mutedrive 10nf 100k v audio 42 v smfilt 15 16 v rfadj v pllout 14 v amtadj fm test circuit TDA7421 14/38
fm section featuring a single conversion configuration, it comprises a multi-stage if limiter whose gain is i 2 c controlled and a quadrature demodulator with detuning and adjacent channel detectors. signal meter and stop station functions are also sup- ported am section am signal is converted by means of up-down configuration (if1 = 10.7mhz, if2 = 450khz) and mw/lw bands are covered. pll section three operating modes are available: pm0 pm1 operating mode 0 0 standby 10 am 0 1 not used 11 fm they are user programmable with the mode pm registers. standby mode it stops all functions. this allows low current con- sumption without loss of information in all regis- ters. the pin lp-out is forced to 0v in power on. all data registers are set to fe (11111110). the oscillator runs even in stand-by mode. fm and am operation the fm or am signal applies to a 32/33 pres- caler, which is controlled by a 5 bit counter (a). the 5 bit register (pc0 to pc4) controls this di- vider. the output of the prescaler connects to a 11 bit divider (b). the 11 bit register (pc5 to pc15) controls the divider b. three state phase comparator the phase comparator generates a phase error signal according to phase difference between f syn and f ref . this phase error signal drives the charge pump current generator. charge pump current generator this stage generates signed pulses of current. the phase error signal decides the duration and polarity of those pulses. the current absolute values are programmable by a0, a1, a2 registers for high current and b0, b1 registers for low current. low noise cmos op-amp an internal voltage divider at pin v ref connects the positive input of the low noise op-amp. the charge pump output connects the negative input. this internal amplifier in cooperation with external components can provide an active filter. the negative input is switchable to three input pins (lpin 1, lpin 2 and lpin 3), to increase the flexibility in application. this feature allows two separate active filters for different applications. a logical "1" in the lpin 1/2 register activates pin lpin 1, otherwise pin lpin 2 is active. while the high current mode is activated lpin 3 is switched on. inlock detector the charge pump is switched in low current mode as the truth table and the related figure shows. currhigh lockena lock (by inlock detector) charge pump current 0 x x low current 1 1 1 low current 1 1 0 high current 1 0 1 high current 1 0 0 high current the charge pump is forced in low current mode when a phase difference of 10-40 usec is reached. a phase difference larger than the programmed values will switch the charge pump immediately in the high current mode. few programmable delays are available for inlock detection. if counter system for am/fm the if counter mode is controlled by ifcm register: ifcm1 ifcm0 function 0 0 not used 0 1 fm mode 1 0 am mode 1 1 not used a sample timer to generate the gate signal for the main counter is built with a 14 bit programmable counter to have the possibility to use any fre- TDA7421 15/38
quency. in fm mode a 6.25 khz, in am mode a 1khz signal is generated. this counter is fol- lowed by an asynchronous divider to generate several sampling times. intermediate frequency main counter (ifmc) this counter is a 13-21 bit synchronous autore- load down-counter. four bits are programmable to have the possibility for an adjust to the fre- quency of the if filter. the counter length is automatically adjusted to the chosen sampling time and the counter mode. at the start the counter will be loaded with a de- fined value which is an equivalent to the divider value (t sample f if ). if a correct frequency is applied to the if counter frequency inputs if-am and if-fm, at the end of the sampling time the main counter is changing its state from 0 to 1fffffh. this is detected by a control logic. the frequency range inside which a successful count results is detected is adjustable setting bits ew 0, 1, 2. up-down counter filter the information coming from the if main counter control logic is shifted into a 5 bit up down counter circuit clocked by the sampling time sig- nal. at the start (rising edge of the ifena signal) the counter is set to 10h and the sstop signal is forced to "1". only when the counter reaches the value 10h - step, sstop goes to "0". sstop will be "1" again, if the counter reaches the value 10h + step. msb lsb function subad bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pll charge pump 00h l p i n1/2 c urrh b1 b0 a3 a2 a1 a0 pll counter 01h pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pll counter 02h pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pll ref counter 03h rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 pll ref counter 04h rc15 rc14 rc13 rc12 rc11 rc10 rc9 rc8 pll lock detect 05h ldena - d3 d2 d1 d0 pm1 pm0 ifc ref counter 06h irc7 irc6 irc5 irc4 irc3 irc2 irc1 irc0 ifc ref counter 07h ifcm1 ifcm0 irc13 irc12 irc11 irc10 irc9 irc8 ifc control 08h ifena - - - - ew2 ew1 ew0 ifc control 09h ifs2 ifs1 ifs0 cf4 cf3 cf2 cf1 cf0 address organization (pll and if counter) ref osc in register r0 ...r15 divider : r pd am in fm in register pc0 ...pc4 counter a prescaler 32/33 register pc5 ... p15 divider : b fref fsyn d96au545 fosc i 2 c bus i 2 c bus i 2 c bus (o/i) fm and am operation (swallow mode) curr high lockena lock charge pump current d96au548 charge pump logic TDA7421 16/38
t tim = (ifrc + 1) / f osc t cnt = (cf + 1697) / f if fm mode t cnt = (cf + 44) / f if am mode counter result succeeded: t tim > t cnt - t err and t tim > t cnt + t err counter result failed: t tim < t cnt + t err or t tim > t cnt - t err where: t tim = if time cycle time t cnt = if counter cycle time t err = discrimination window (controlled by the ew registers) the precision of the measurements is adjustable by controlling the discrimination window. this is adjustable by programming the control registers ew0...ew2. the measurement time per cycle is adjustable by setting the register ifs0 - ifs2. the center frequency of the discrimination win- dow is adjustable by the control register "cf0" to "cf4". the available values are reported in dat- abyte specification i 2 c bus interface general description the TDA7421 supports the i 2 c bus protocol. this protocol defines the devices sending data into the bus as transmitter and the receiving device as the receiver. the device that controls the transfer is a master and the device being controlled is the slave. the master will always initiates data transfer and pro- vide the clock to transmit or receive operations. data transition data transition on the sda line must only occur when the clock scl is low. sda transitions while scl is high will be interpreted as start or stop condition. start condition phase comparator t tim t cnt -t err succeeded t cnt +t err failed failed d96au551 TDA7421 17/38
a start condition is defined by a high to low transition of the sda line while scl is at a stable high level. this start condition must precede any command and initiate a data transfer onto the bus. the TDA7421 continuously monitors the sda and scl lines for a valid start and will not re- sponse to any command if this condition has not been met. stop condition a stop condition is defined by a low to high transition of the sda while the scl line is at a stable high level. this condition terminate the communication between the devices and forces the bus interface of the TDA7421 into the initial condition. acknowledge indicates a successful data transfer. the trans- mitter will release the bus after sending 8 bit of data. during the 9th clock cycle the receiver will pull the sda line to low level to indicate it has received the eight bits of data correctly. data transfer during data transfer the TDA7421 samples the sda line on the leading edge of the scl clock, therefore, for proper device operation the sda line must be stable during the scl low to high transition. device addressing to start the communication between two devices, the bus master must initiate a start instruction se- quence, followed by an eight bit word corre- sponding to the address of the device it is ad- dressing. the most significant 6 bits of the slave address identify the device type. the TDA7421 device code is fixed as "110001". the next significant bit is used either to address the tuner section (1) or the pll section (0) of the chip. following a start condition the master sends slave address word; the TDA7421 will "acknow- ledge" after this first transmission and wait for a second word (the word address field). this 8 bit address field provides an access to any of the 8 internal addresses. upon receipt of the word address the TDA7421 slave device will re- spond with an "acknowledge". at this time, all the following words transmits to the TDA7421 will be considered as data. the internal address will be automatically incre- mented. after each word receipt the TDA7421 will answer with an "acknowledge". the interface protocol comprises: C a subaddress byte C a sequence of data (n-bytes + acknowledge) C a stop condition (p) C a start condition (s) C a chip address byte register name function pc programmable counter for vco frequency rc reference counter pll irc reference counter if ifcm if counter mode ew frequency error window ifena enable if counter cf center frequency if counter ifs sampling time if counter pm stby, fm, am, am swallow mode (pll mode) d programmable delay for lock detector lpin1/2 loop filter input select a charge pump high current b charge pump low current ldena lock detector enable currh set current high control register function TDA7421 18/38
d95au378 t high t r t low t r scl sda in sda out t su-sta t hd-sta t hd-dat t sd-dat t subtop t txt t aa t dh i 2 c bus timing diagram 11-21 bit counter cf-register 3 bit counter 14 bit counter zd ifs-register ifc-register ew-register up/down counter ifena if-am if-fm osc d97au809 if counter block diagram TDA7421 19/38
s 1 1 0 0 0 1 0 0 ack ack ack p msb lsb msb lsb msb lsb chip address d96au549 t2 i subaddress data 1 to data n t1 t0 a3 a2 a1 a0 frame example for addressing the pll part: d96au550 s 1 1 0 0 0 1 1 0 ack ack ack p msb lsb msb lsb msb lsb chip address 0i subaddress data 1 to data n 00 a3 a2 a1 a0 for the tuner part: ack = acknowledge s = start p = stop i = page mode t2, t1, t0 = used in test mode (for pll only, for tuner addressing they must be 0) a3, a2, a1, a0 = mode selection tuner subaddress msb lsb function x x x i a3 a2 a1 a0 0 0 0 0 status 0 0 0 1 fm stop station / fm if agc 0 0 1 0 fm smeter slider 0 0 1 1 am agc1 / am stop station 0 1 0 0 ift1 / ift2 0 1 0 1 front end adjustment 0 1 1 0 fm demodulator adjustment 0 1 1 1 fm if buffers 1 0 0 0 fm audio mute gain / fm soft mute 1 0 0 1 fm hole detector / fm detuning 0 page mode disabled 1 page mode enabled 0 0 0 must be "0" pll subaddress msb lsb function t3 t2 t1 i a3 a2 a1 a0 0000charge pump control 0001pll c ounter 1 (lsb) 0010pll c ounter 2 (msb) 0011pll reference c ounter 1 (lsb) 0100pll reference c ounter 2 (msb) 0101pll lockdetector control and pll m ode select 0110ifc reference c ounter 1 (lsb) 0111ifc refere nce counter 2 (msb) and ifc mode select 1000if counter control 1 1001if counter control 2 0 page mode disabled 1 page mode enabled t1, t2, t3 are used for testing the pll, in application mode they have to be "0". TDA7421 20/38
pll counter 1 (lsb) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000lsb = 0 00000001lsb = 1 00000010lsb = 2 all combinations allowed 11111100lsb = 252 11111101lsb = 253 11111110lsb = 254 11111111lsb = 255 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 bit name subaddress = 01h pll data byte specification chargepump control msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 0000high current = 0ma 0001high current = 0.5ma 0010high current = 1.0ma 0011high current = 1.5ma 0100high current = 2.0ma 0101high current = 2.5ma 0110high current = 3.0ma 0111high current = 3.5ma 1000high current = 4.0ma 1001high current = 4.5ma 1010high current = 5.0ma 1011high current = 5.5ma 1100high current = 6.0ma 1101high current = 6.5ma 1 1 1 0 high current = 7.0ma 1111high current = 7.5ma 0 0 low current = 0 m a 0 1 low current = 15 m a 1 0 low current = 100 m a 1 1 low current = 115 m a 0 select low current 1 select high current 0 select loop filter 1 1 select loop filter 2 lpin1/2 currh b1 b0 a3 a2 a1 a0 subaddress = 00h TDA7421 21/38
pll counter 2 (msb) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000 msb = 0 00000001 msb = 256 00000010 msb = 512 all combinations allowed 11111100 msb = 64768 11111101 msb = 65024 11111110 msb = 65280 11111111 msb = 65536 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 bit name subddress = 02h swallow mode: f vco /f syn = lsb + msb + 32 pll reference counter 1 (lsb) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000lsb = 0 00000001lsb = 1 00000010lsb = 2 all combinations allowed 11111100lsb = 252 11111101lsb = 253 11111110lsb = 254 11111111lsb = 255 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 bit name subaddress =03h pll reference counter 2 (msb) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000 msb = 0 00000001 msb = 256 00000010 msb = 512 all combinations allowed 11111100 msb = 64768 11111101 msb = 65024 11111110 msb = 65280 11111111 msb = 65536 rc15 rc14 rc13 rc12 rc11 rc10 rc9 rc8 bit name subddress = 04h f osc /f ref = lsb + msb + 1 TDA7421 22/38
lock detector & pll mode control msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 0 0 pll standby mode 0 1 pll am 1 0 not used 1 1 pll fm mode 0 0 pd phase difference threshold 10ns 0 1 pd phase difference threshold 20ns 1 0 pd phase difference threshold 30ns 1 1 pd phase difference threshold 40ns 0 0 not used in application mode 0 1 activation delay = 4 f ref 1 0 activation delay = 6 f ref 1 1 activation delay = 8 f ref 0 no lock detector controlled chargepump 1 lock detector controlled chargepump ldena d3 d2 d1 d0 pm1 pm0 bit name subaddress = 05h if counter reference control 1 (lsb) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000lsb = 0 00000001lsb = 1 00000010lsb = 2 all combinations allowed 11111100lsb = 252 11111101lsb = 253 11111110lsb = 254 11111111lsb = 255 irc7 irc6 irc5 irc4 irc3 irc2 irc1 irc0 bit name subaddress = 06h TDA7421 23/38
if counter reference control 2 (msb) and if counter mode select msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000 msb = 0 00000001 msb = 256 00000010 msb = 512 all combinations allowed 1 1 1 1 0 1 msb = 15616 1 1 1 1 1 0 msb = 15872 1 1 1 1 1 1 msb = 16128 0 0 not used in application mode 0 1 if counter fm mode 1 0 if counter am mode 1 1 not used ifcm1 ifcm0 irc13 irc12 irc11 irc10 irc9 irc8 bit name subaddress = 07h f osc /f tim = lsb + msb + 1 if counter control 1 msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 dont use 0 0 1 dont use 0 1 0 dont use 0 1 1 ew delta f = 6.25khz (fm); 1khz (am) 1 0 0 ew delta f = 12.5khz (fm); 2khz (am) 1 0 1 ew delta f = 25khz (fm); 4khz (am) 1 1 0 ew delta f = 50khz (fm); 8khz (am) 1 1 1 ew delta f = 100khz (fm); 16khz (am) 0 if counter disabled / stand by 1 if counter enabled ifena ew2 ew1 ew0 bit name subaddress = 08h TDA7421 24/38
if counter control 2 msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 fcenter = 10.60000mhz (fm) 448khz (am) 0 0 0 0 1 fcenter = 10.60625mhz (fm) 449khz (am) 0 0 0 1 0 fcenter = 10.61250mhz (fm) 450khz (am) 0 0 0 1 1 fcenter = 10.61875mhz (fm) 451khz (am) 0 0 1 0 0 fcenter = 10.62500mhz (fm) 452khz (am) 0 0 1 0 1 fcenter = 10.63125mhz (fm) 453khz (am) 0 0 1 1 0 fcenter = 10.63750mhz (fm) 454khz (am) 0 0 1 1 1 fcenter = 10.64375mhz (fm) 455khz (am) 0 1 0 0 0 fcenter = 10.65000mhz (fm) 456khz (am) 0 1 0 0 1 fcenter = 10.65625mhz (fm) 457khz (am) 0 1 0 1 0 fcenter = 10.66250mhz (fm) 458khz (am) 0 1 0 1 1 fcenter = 10.66875mhz (fm) 459khz (am) 0 1 1 0 0 fcenter = 10.67500mhz (fm) 460khz (am) 0 1 1 0 1 fcenter = 10.68125mhz (fm) 461khz (am) 0 1 1 1 0 fcenter = 10.68750mhz (fm) 462khz (am) 0 1 1 1 1 fcenter = 10.69375mhz (fm) 463khz (am) 1 0 0 0 0 fcenter = 10.70000mhz (fm) 464khz (am) 1 0 0 0 1 fcenter = 10.70625mhz (fm) 465khz (am) 1 0 0 1 0 fcenter = 10.71250mhz (fm) 466khz (am) 1 0 0 1 1 fcenter = 10.71875mhz (fm) 467khz (am) 1 0 1 0 0 fcenter = 10.72500mhz (fm) 468khz (am) 1 0 1 0 1 fcenter = 10.73125mhz (fm) 469khz (am) 1 0 1 1 0 fcenter = 10.73750mhz (fm) 470khz (am) 1 0 1 1 1 fcenter = 10.74375mhz (fm) 471khz (am) 1 1 0 0 0 fcenter = 10.75000mhz (fm) 472khz (am) 1 1 0 0 1 fcenter = 10.75625mhz (fm) 473khz (am) 1 1 0 1 0 fcenter = 10.76250mhz (fm) 474khz (am) 1 1 0 1 1 fcenter = 10.76875mhz (fm) 475khz (am) 1 1 1 0 0 fcenter = 10.77500mhz (fm) 476khz (am) 1 1 1 0 1 fcenter = 10.78125mhz (fm) 477khz (am) 1 1 1 1 0 fcenter = 10.78750mhz (fm) 478khz (am) 1 1 1 1 1 fcenter = 10.79375mhz (fm) 479khz (am) 0 0 0 tsample = 20.48ms (fm mode); 128ms (am; mode) 0 0 1 tsample = 10.24ms (fm mode); 64ms (am; mode) 0 1 0 tsample = 5.12ms (fm mode); 32ms (am; mode) 0 1 1 tsample = 2.56ms (fm mode); 16ms (am; mode) 1 0 0 tsample = 1.28ms (fm mode); 8ms (am;mode) 1 0 1 tsample = 640 m s (fm mode); 4ms (am;mode) 1 1 0 tsample = 320 m s (fm mode); 2ms (am; mode) 1 1 1 tsample = 160 m s (fm mode); 1ms (am; mode) ifs2 ifs1 ifs0 cf4 cf3 cf2 cf1 cf0 bit name subaddress = 09h TDA7421 25/38
msb lsb function subad bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 status 00h t e ston fm mute fmadj fmhigh amster eo amseek / fm recseek am/fm/ stby am/fm/ stby fm stop station/ fm if agc 01h fag2 fag1 fag0 fss4 fss3 fss2 fss1 fss0 fm smeter slider 02h fsl4 fsl3 fsl2 fsl1 fsl0 - - - am agc1/am stop station 03h ass3 ass2 ass1 ass0 aag3 aag2 aag1 aag0 ift1/ift2 04h t2a3 t2a2 t2a1 t2a0 t1a3 t1a2 t1a1 t1a0 front end adjustment 05h ana3 ana2 ana1 ana0 rfa3 rfa2 rfa1 rfa0 fm demodulator adjustment 06h sdd dem6 dem5 dem4 dem3 dem2 dem1 dem0 fm if buffers 07h fbl3 fbl2 fbl1 fbl0 fbh3 fbh2 fbh1 fbh0 fm soft mute/ fm audio mute gain 08h fsm3 fsm2 fsm2 fsm0 - aum2 aum1 aum0 fm hole detector /fm detuning detector 09h bwm2 bwm1 bwm0 hdm4 hdm3 hdm2 hdm1 hdm0 tuner data byte specification address organization (tuner am/fm) TDA7421 26/38
status (subaddress 00h) msb lsb function s7 s6 s5 s4 s3 s2 s1 s0 teston fmmute fmadj fmhigh am stereo am seek/fm recseek am/fm/ stby am/fm/ stby x x x x x x 0 0 stand-by 0 0 0 0 x 0 0 1 fm on, reception, deep mute 0 0 0 0 x 1 0 1 fm on, seek, deep mute 0 0 0 1 x 0 0 1 fm on, reception, shallow mute 0 0 0 1 x 1 0 1 fm on,seek shallow mute 0 0 1 x x x 0 1 fm on for demod adjustm, demod on 0 1 1 x x x 0 1 fm on for demod adjustment demod muted 0 x x x 0 0 1 0 am on (japan), reception, ifc out selected 0 x x x 0 1 1 0 am on (japan), seek, ifc out selected 0 x x x 1 0 1 0 am on (japan), reception am stereo out selected 0 x x x 1 1 1 0 am on (japan), seek, am stereo out selected 0 x x x 0 0 1 1 am on (eu, us), reception, ifc out selected 0 x x x 0 1 1 1 am on (eu, us), seek, ifc out selected 0 x x x 1 0 1 1 am on (eu, us), reception am stereo out selected 0 x x x 1 1 1 1 am on (eu, us), seek, am stereo out selected 1 x x pll test output enabled am turn on sequence at power on: it is necessary to cycle through st-by for a correct opera- tion. TDA7421 27/38
fm stop station / fm if agc (subaddress 01h) msb lsb function fag2 fag1 fag0 fag4 fss3 fss2 fss1 fss0 fmifagc msb fmifagc fmifagc lsb fmstop station msb fmstop station fmstop station fmstop station fmstop station lsb fm stop station threshold 0 0 0 0 0 maximum sensitivity x x xxx 1 1 1 1 1 minimum sensitivity all combinations allowed fm if agc threshold 0 0 0 maximum sensitivity xxx 1 1 0 minimum sensitivity 1 1 1 keying agc disabled all combinations allowed fm smeter slider (subaddress 02h) msb lsb function fsl4 fsl3 fsl2 fsl1 fsl0 fmsmeters lider msb fmsmeterslider f msmeter slider lsb fm smeter slider threshold (mv) 0 0 0 0 0 300 (baseline) 0 0 0 0 1 348.4 (+48.4) 0 0 0 1 0 396.8 (+96.8) 0 0 1 0 1 493.6 (+193.6) 0 1 0 0 0 687.2 (+387.2) 1 0 0 0 0 1074.4 (+774.4) 1 1 1 1 1 1800 (top) all combinations allowed TDA7421 28/38
am stop station / am agc1 (subaddress 03h) msb lsb function ass3 ass2 ass1 ass0 aag3 aag2 aag1 aag0 amstopsta tion msb amstopstation amstopsta tion lsb amagc1 msb amagc1 amagc1 amagc1 lsb am agc1 threshold 0 0 0 0 maximum sensitivity x xxx 1 1 1 1 minimum sensitivity all combinations allowed am stop station threshold 0 0 0 0 maximum sensitivity xxxx 1 1 1 1 minimum sensitivity all combinations allowed ift1/ ift2 (subaddress 04h) msb lsb function t2a3 t2a2 t2a1 t2a0 t1a3 t1a2 t1a1 t1a0 ift2 adjust msb ift2 adjust ift2 adjust ift2 adjust lsb ift1 adjust msb ift1 adjust ift1 adjust ift1 adjust lsb adjustment capacitor 00000 0001c ift1 00102c ift1 01004c ift1 10008c ift1 111115c ift1 all combinations allowed 0000 0 0001 ci ft2 0010 2ci ft2 0100 4ci ft2 1000 8ci ft2 1111 15ci ft2 all combinations allowed TDA7421 29/38
front end adjustment (subaddress 05h) msb lsb function ana3 ana2 ana1 ana0 rfa3 rfa2 rfa1 rfa0 ant adjustm msb ant adjustm ant adjustm ant adjustm lsb rf adjustm msb rf adjustm rf adjustm rf adjustm lsb voffset rf varicap / vpll x0000 0001-3.6% 0010-7.2% 0 1 0 0 -14.3% 0111-25% 10013.6% 10107.2% 110014.3% 111125% all combinations allowed v offset antenna varicap / vpll x000 0 0001 -3.6% 0010 -7.2% 0 1 0 0 -14.3% 0111 -25% 1001 3.6% 1010 7.2% 1100 14.3% 1111 25% all combinations allowed TDA7421 30/38
fm demodulator adjustment (subaddress 06h) msb lsb function sdd dem6 dem5 dem4 dem3 dem2 dem1 dem0 sd disable demadj msb demadj demadj demadj demadj demadj demadj lsb adjustment capacitor 00000000 0000001c demod 00000102c demod 00001004c demod 00010008c demod 001000016c demod 010000032c demod 100000064c demod 1111111127c demod all combinations allowed sd disable 0 sd enabled 1 sd disabled (high impedance output) fm if buffers (subaddress 07h) msb lsb function fbl3 fbl2 fbl1 fbl0 fbh3 fbh2 fbh1 fbh0 buff2 gain msb buff2 gain buff2 gain buff2 gain lsb buff1 gain msb buff1 gain msb buff1 gain buff1 gain lsb buffer 1 gain (db) 000019.5 000115.5 001016.5 010017.5 100018.5 all else not allowed buffer 2 gain (db) 0000 8 0001 4 0010 5 0100 6 1000 7 all else not allowed TDA7421 31/38
fm soft mute / fm audio mute gain (subaddress 08h) msb lsb function fsm3 fsm2 fsm1 fsm0 aum2 aum1 aum0 fmsoft mute msb fmsoftmute fmsoftmute fmsoftmute lsb buff1 gain msb buff1 gain buff1 gain lsb fm soft mute threshold 0 0 0 0 maximum sensitivity xxxx 1 1 1 1 minimum sensitivity all combinations allowed audio max mute atten. (db) with bit fmhigh byte 0 = 1 0 0 1 -2.5 010-5 1 0 0 -7.5 011-10 110-12.5 111-15 audio max mute atten. (db) with bit fmhigh byte 0 = 0 001-17.5 010-20 100-22.5 011-25 110-27.5 111-30 all else not allowed fm hole detector / fm detuning detector (subaddress 09h) msb lsb function bwm2 bwm1 bwm0 hdm4 hdm3 hdm2 hdm1 hdm0 bw msb bw bw lsb hole det msb hole det hole det hole det hole det lsb muting sensitivity 0 0 0 0 0 minimum (deep hole) xxxxx 1 1 1 1 1 maximum (shallow hole) all combinations allowed reception detuning mute range 0 0 1 10 (khz) 0 1 0 15 (khz) 1 0 0 30 (khz) all else not allowed seek clamping window 0 0 0 minimal window x x x intermediate values 1 1 1 maximal window all combinations allowed TDA7421 32/38
from cx - see schematic (part d) from lpout - pin 17 rfvcc oscvcc 30 db differential g ain 6p 10n 6p 3p mix_in 50 1k t1 10n fm in sp 0 22p 100k 0 0 1k5 4.7n 100n 0 0 4.7n tp20 5k6 1m 1k5 15p 15p 10.25mhz 10n 10u + 10n 3.3p l2 100k 100k 470 68p 15p 1k8 22u + 5p am mix1 in- 1 am mix1 in+ 2 fm mix in- 3 fm mix in+ 4 fm rf agc in 5 fm agc out 6 rf gnd 7 vco b 8 vco e 9 osc gnd 10 xtal d 11 xtal 12 osc vcc 13 fm ant adj 14 fm rf adj 15 pll vcc 16 1k5 47n tp21 evaluation board schematic circuit (part a) from rx i2cbus +5v 33k 2.7n 4k3 33n 1n 18k 4.7n 1 2 3 4 5 22n 22n 10u + tp18 3.3n + tp22 2.2u + am st tp19 lp out 17 lp in1 18 lp in2 19 lp in3 20 pll vref 21 pll gnd 22 sleep 23 sda 24 scl 25 dig vdd 26 dig gnd 27 ifc sstop/am st 28 cln gnd 29 if2 gnd 30 am agc2 tc 31 am det 32 evaluation board schematic circuit (part b) TDA7421 33/38
see schematic (part d) if2vcc if1vcc 120p tp17 10n 22u + audio out 5k6 l6 22n 2.2u + 22n 0 cf4 10.7mhz 50 fmif2 0 1u + tp16 tp13 100k tp11 1mh am bpf 33 am ref 34 am if2 in 35 if2 vcc 36 fm quad- 37 fm quad+ 38 audio out 39 fm sd/am sd 40 fm/am s-meter 41 fm mute drive 42 fm bw tc 43 if1 gnd 44 fm lim in- 45 fm lim in+ 46 if1 vcc 47 fmif amp2out 48 tp12 tp14 tp15 evaluation board schematic circuit (part c) from pin 1 - am mix in- from pin 35 - am if2 in from pin 48 - fmif amp2 out rfvcc rfvcc rfvcc rfvcc 10n 50 am in 68uh 68uh 1k 1mh 27 100n 82p 1m 1u + tp10 1 0 t3 tp6 1 0 22n 22n 1.5n 4k7 0 10n tp3 1 tp4 1 0 00 0 f2 450khz 0 tp7 1 amif tp8 1 tp9 1 f3 10.7mhz 22n 1u + 2k7 3p 470 0 0 0 100n 0 cf1 10.7mhz 50 0 fmif1 27 50 15p 10n 120p 82p 18p 22n 10n 0 0 1u + 4k7 t2 tp1 1 tp2 1 tp5 1 amamp + 0 68p am agc1 pin 64 fmif amp2in- 49 fmif amp2in+ 50 fmif amp1out 51 fmif amp1 in- 52 fmif amp1 in+ 53 am mix2 out- 54 am mix2 out+ 55 rf vcc 56 am mix2 in- 57 am mix2 in+ 58 fm if agc in 59 mix out- 60 mix out+ 61 am agc1 rf amp 63 am agc1 tc 62 evaluation board schematic circuit (part d) TDA7421 34/38
if1vcc & if2 vcc gnd +vs supply volta g e (12v) ground path pllvcc rfvcc oscvcc +5v 10u + 100n l4916 gnd gnd 6 gnd 7 gnd 8 out 8.5v 4 +vs 1 f. c. 2 n.c. 3 220n 100u + mr1 47u + 220n 100n 10 10 10 10 jp1 l78l05a vo 1 gnd 2 gnd 3 nc 4 nc 5 gnd 6 gnd 7 vin 8 220n 5 evaluation board schematic circuit (part e) notes: - the components shown on the evaluation board schematic without the part value, are required only for measurements between intermediate input/outputs: - parts description: cf1 ceramic filter 10.7mhz, 180khz bw cf3-cf4 ceramic filter 10.7mhz, 150khz bw cf2 ceramic filter 450khz, 6khz bw t1 fm rf transformer unloaded q= 103 3-1= 3 1/2t - 6-4= 1t 0.12 f 2uew c tuning (3-1)= 24pf @ 100mhz t2 am/fm if1 transformer unloaded q= 70 1-3= 13t - 1-5= 6 1/2t - 5-3= 6 1/2t - 4-6= 2t 0.08 f 2uew c int (1-2) = c int (2-3) = 82pf; c ext (1-3) = 10pf t3 am if2 transformer unloaded q= 40 1-3= 178t - 1-2= 89t - 2-3= 89t - 4-6= 33t 0.05 f 2uew c int (1-3) = 180pf; c ext (1-3) = 20pf l2 oscillator coil unloaded q= 80 6-4= 2 1/2t 0.12 f 2uew c tuning (6-4)= 36.8pf @ 100mhz l6 demodulator coil unloaded q= 35 6-4= 27t 0.1 f 2uew c int (4-6)= 47pf; c ext (4-6) = 13.5pf TDA7421 35/38
field strength (dbu) t. h. d . ( %) fin= 98.1mhz +/-75khz fm= 1khz 20hz - 20khz filter vs= 8v fm thd response (db) field strength ( dbu ) vs= 8v fin= 1mhz m= 30% fm= 1khz 20hz - 20khz filter am s+n/n t.h .d. ( %) field strength ( dbu ) fin= 1mhz m= 30% fm= 1khz 20hz - 20khz filter vs= 8v am thd field strength (dbu) response (db) vs= 8v fm= 1khz 20hz - 20khz filter fin= 98.1mhz +/- 75khz without de-emphasis fm s+n/n TDA7421 36/38
a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b tqfp64 l l1 seating plane 0.10mm tqfp64 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.18 0.23 0.28 0.007 0.009 0.011 c 0.12 0.16 0.20 0.0047 0.0063 0.0079 d 12.00 0.472 d1 10.00 0.394 d3 7.50 0.295 e 0.50 0.0197 e 12.00 0.472 e1 10.00 0.394 e3 7.50 0.295 l 0.40 0.60 0.75 0.0157 0.0236 0.0295 l1 1.00 0.0393 k 0 (min.), 7 (max.) TDA7421 37/38
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics ? 1998 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. TDA7421 38/38

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